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(Diode test circuit model.) |
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| - | Diode test circuit model. | + | Diode test circuit model from Convex Optimization & Euclidean Distance Geometry, Chapter 8.1. |
| + | (a) Large signal diode model: | ||
| + | 1) junction capacitance C_j is small enough to ignore for audio applications, | ||
| + | 2) diffusion capacitance C_d whose polarization (+) indicates significant capacitance only for positive bias voltage v_d, | ||
| + | 3) static semiconductor & contact resistivity R_d a.k.a parasitic resistivity. | ||
| + | (b) Figure 211b unbalancing and consolidation to help explain high median impedance of diffusion capacitor. | ||
| + | [[https://www.convexoptimization.com/TOOLS/Sedra.pdf PSPICE DEVICE MODELS & SIMULATION]] | ||
Revision as of 22:12, 16 January 2025
Diode test circuit model from Convex Optimization & Euclidean Distance Geometry, Chapter 8.1. (a) Large signal diode model: 1) junction capacitance C_j is small enough to ignore for audio applications, 2) diffusion capacitance C_d whose polarization (+) indicates significant capacitance only for positive bias voltage v_d, 3) static semiconductor & contact resistivity R_d a.k.a parasitic resistivity. (b) Figure 211b unbalancing and consolidation to help explain high median impedance of diffusion capacitor. [PSPICE DEVICE MODELS & SIMULATION]
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| (current) | 15:39, 16 January 2025 | Ranjelin (Talk | contribs) | 3510×3040 | 784 KB | Diode test circuit model. |
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